JEDEC JEP156A – CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION
This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products.
Product Details
Published:
03/01/2018
Number of Pages:
24
File Size:
1 file , 85 KB
Note:
This product is unavailable in Russia, Ukraine, Belarus
