JEDEC JEP159A

Description

JEDEC JEP159A – PROCEDURE FOR THE EVQLUQTION OF LOW-k/METAL INTER/INTRA-LEVEL DIELECTRIC INTEGRITY

This document is intended for use in the semiconductor IC manufacturing industry and provides reliability characterization techniques for low-k inter/intra level dielectrics (ILD) for the evaluation and control of ILD processes. It describes procedures developed for estimating the general integrity of back-end-of-line (BEOL) ILD. Two basic test procedures are described, the Voltage-Ramp Dielectric Breakdown (VRDB) test, and the Constant Voltage Time-Dependent Dielectric Breakdown stress (CVS). Each test is designed for different reliability and process evaluation purposes. This document also describes robust techniques to detect breakdown and TDDB data analysis.

Product Details

Published:

07/01/2015

Number of Pages:

30

File Size:

1 file , 510 KB

Redline File Size:

2 files , 4.6 MB

Note:

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