JEDEC JESD203
$31.00
STANDARD TEST LOADS FOR DUAL-SUPPLY LEVEL TRANSLATION DEVICES
Published by | Publication Date | Number of Pages |
JEDEC | 11/01/2005 | 9 |
Description
JEDEC JESD203 – STANDARD TEST LOADS FOR DUAL-SUPPLY LEVEL TRANSLATION DEVICES
This standard defines ac test loads for dual-supply level translation devices. Uniform test loads enable easy comparison of electrical parameters of dual-supply level translation devices across functions, logic families and IC suppliers. This standard is only intended to apply to devices released subsequent to the publication of this document.
Product Details
- Published:
- 11/01/2005
- Number of Pages:
- 9
- File Size:
- 1 file , 86 KB
- Note:
- This product is unavailable in Russia, Ukraine, Belarus