JEDEC JESD235

Description

The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 28b data bus operating at DDR data rates.

Product Details

Published:

10/01/2013

Number of Pages:

124

File Size:

1 file , 2.3 MB

Note:

This product is unavailable in Russia, Ukraine, Belarus