JEDEC JESD78E

Description

JEDEC JESD78E – IC LATCH-UP TEST

This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits. The purpose of this standard is to establish a method for determining IC latch-up characteristics and to define latch-up detection criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies.

This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880.

Product Details

Published:

04/01/2016

Number of Pages:

32

File Size:

1 file , 750 KB

Note:

This product is unavailable in Russia, Ukraine, Belarus