JEDEC JESD8-8 – ADDENDUM No. 8 to JESD8 – STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS
This standard is a result of a major effort by the JC-16 Committee to develop a high performance CMOS-based interface suitable for high speed main memory applications in excess of 125 MHz.
Product Details
Published:
08/01/1996
Number of Pages:
18
File Size:
1 file , 1.2 MB
Note:
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