JEDEC JESD47K – STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.
Product Details
Published:
08/01/2018
Number of Pages:
34
File Size:
1 file , 660 KB
Note:
This product is unavailable in Russia, Ukraine, Belarus
